上機考 nand

odule top;

wire a, A, b, B, c, C, d, D, F, F1, F2, F3, F4;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

nand S1(a, A, B);
nand S2(b, B, B);
nand S3(c, C, C);
nand S4(d, D, D);
nand C1(F1, a ,b , C);
nand C2(F2, a, B, C);
nand C3(F3, A, C, D);
nand C4(F4, A,b, C);
nand o1(F, F4, F2, F3, F1);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule