12/2

module top;

wire A,B,C,D,E,F;
system_clock #1600 clock1(A);
system_clock #800 clock2(B);
system_clock #400 clock3(C);
system_clock #200 clock4(D);

not z1(a,A);
not z2(b,B);
not z3(c,C);
not z4(d,D);
and X1(F1, C, D);
and X2(F2, a, b, D);
and X3(F3, B, c, d);
and X4(F4, A, c, d);
or W(F, F1, F2, F3, F4);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule